1. Field of the Invention
The present invention relates to a semiconductor device having a large power element, such as a power transistor.
2. Description of the Related Art
A semiconductor device having a packaged chip, such as a semiconductor integrated circuit (IC), is currently manufactured and utilized in various types of electronic devices. In this semiconductor device, terminals (pads) of a semiconductor chip main body are packaged so as to have external terminals to be used for connection with an external circuit.
Such a semiconductor chip main body is provided with a plurality of connection pads. The pads are connected to the external terminals, respectively. A method using lead terminals has been employed as a method for connecting the pads to the external terminals. However, a connection method using a ball grid array (BGA) structure has come into widespread use.
A chip-size package (CSP), which is substantially equal in outer dimension to the semiconductor chip main body, is implemented by use of the connection method using a BGA structure. In the CSP, pads opposing the respective pads or the semiconductor chip main body are provided on one side of a substrate, and ball-shaped external electrodes are provided in a two-dimensional grid pattern on the other surface of the substrate. On the substrate, the respective pads and the respective external electrodes are individually connected together.
In this CSP, the external electrodes are formed from spherical solder bumps and arranged two-dimensionally over essentially the entire lower surface of the semiconductor device. Consequently, the external electrodes can be formed to a compact, slim size close to the size of the chip. Further, the external electrodes can be mounted on the surface of a printed wiring board.
A semiconductor device of T-BAG structure utilizing a carrier tape is also employed (see Patent Document 1). In this semiconductor device or T-BAG structure, a conductive layer made of copper foil and another conductive layer made of conductive paint are provided on a rectangular carrier tape, and an IC chip main body is placed at and conductively connected to the center of the carrier tape. By means of the conductive connection, signal bumps are provided in a two-dimensional pattern on essentially the entire lower surface, and ground bumps are provided along an outer edge section.
However, in the CSP using the conventional connection method using a BGA structure, a plurality of external electrodes are arranged in a grid pattern. The length of the wires extending from the external electrodes located close to the center of the grid pattern to the pads of the IC chip main body becomes long. Therefore, additional wiring resistance is added to the wires, which is responsible for an increase in the loss of the external electrodes through which large current for the power element flows, or deterioration of a control characteristic of the power element.
In the semiconductor device with a T-BAG structure described as disclosed in Japanese Patent No. 3147165, two conductive layers must be provided on the carrier tape, which ends up increasing the cost. since only a ground electrical path (or a power electrical path) can be formed with low resistance by said structure, it is not appropriate to adopt such manner for the purpose of lowering the resistance of an output circuit of the power element.